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74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
February 1992 Revised June 2001
74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVQ374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flipflops.
Features
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 s 4 kV minimum ESD immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory address registers
Ordering Code:
Order Number 74LVQ374SC 74LVQ374SJ 74LVQ374QSC Package Number M20B M20D MQA20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description Inputs Dn H L X CP Outputs OE L L H
L = LOW Voltage Level Z = High Impedance

X
On H L Z
H = HIGH Voltage Level X = Immaterial = LOW-to-HIGH Transition
(c) 2001 Fairchild Semiconductor Corporation
DS011360
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74LVQ374
Functional Description
The LVQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVQ374
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 400 mA -65C to +150C 300 mA
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 3.0V 125 mV/ns 2.0V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN IOLD IOHD ICC IOZ Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum 3-STATE Leakage Current VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage 3.6 0.25 2.5 A VCC (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.6 3.6 3.6 3.6 4.0 0.002 TA = +25C Typ 1.5 1.5 2.99 2.0 0.8 2.9 2.58 0.1 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 0.8 2.9 2.48 0.1 0.44 1.0 36 -25 40.0 V V V V V V A mA mA A VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH (Note 3) IOH = -12 mA IOUT = 50 A VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 3.3 3.3 3.3 3.3 0.5 -0.3 1.7 1.6 0.8 -0.8 2.0 0.8 V V V V (Note 6)(Note 7) (Note 6)(Note 7) (Note 6)(Note 8) (Note 6)(Note 8) Units Conditions
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75 for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
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74LVQ374
AC Electrical Characteristics
TA = +25C Symbol fMAX tPLH tPHL tPZL tPZH tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 9) CP to On Output Disable Time Parameter Maximum Clock Frequency Propagation Delay CP to On Output Enable Time VCC (V) 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 Min 55 75 3.0 3.0 3.0 3.0 1.0 1.0 11.4 9.5 11.4 9.5 11.4 9.5 1.0 1.0 18.3 13.0 18.3 13.0 20.4 14.5 1.5 1.5 CL = 50 pF Typ Max TA = -40C to +85C CL = 50 pF Min 50 70 3.0 3.0 3.0 3.0 1.0 1.0 19.0 13.5 19.0 13.5 21.0 15.0 1.5 1.5 Max MHz ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
TA = +25C Symbol Parameter VCC (V) tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width, HIGH or LOW 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 Typ 0 0 0 0 2.4 2.0 CL = 50 pF 4.0 3.0 1.5 1.5 5.0 4.0 TA = 40C- to +85C CL = 50 pF Guaranteed Minimum 4.5 3.0 1.5 1.5 6.0 4.0 ns ns ns Units
Capacitance
Symbol CIN CPD (Note 10) Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 39 Units pF pF VCC = Open VCC = 3.3V Conditions
Note 10: CPD is measured at 10 MHz.
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74LVQ374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74LVQ374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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